1. Field of the Invention
The present invention relates to the structure of a semiconductor integrated circuit.
2. The Prior Art
In the manufacture of a semiconductor integrated circuit device, the process of integrating elements forming a pnpn structure, such as a thyristor, into the circuit in a lateral arrangement comprises forming an n type epitaxial layer on a p type silicon semiconductor substrate, then forming a first and a second p type region on said epitaxial layer, followed by forming an n type region in said second p type region. In such a pnpn structure, a parastic transistor may be formed by said p type region, the n type epitaxial layer and the p type silicon semiconductor substrate. The formation of the parastic transistor causes the phenomenon that when the pn junction between the p type region and the n type epitaxial layer is forward-biased, the parastic transistor turns on to allow a leakage current to flow from the p type region via the n type region to the p type silicon semiconductor substrate.
In order to overcome the above-mentioned disadvantage, conventionally, an n.sup.+ type buried layer was formed between a portion of said n type epitaxial layer enclosed by a dielectric isolation region and said p type silicon semiconductor substrate. This was done to reduce the current amplification factor of the parastic transistor so as to lessen the possibility of the transistor turning on. However, with this conventional structure, the integrated circuit cannot withstand a high voltage. In addition, a sufficiently deep dielectric isolation region is required for traversing the epitaxial layer. On the other hand, if the dielectric isolation region has a large depth, it has an increased surface area in proportion to the depth, so that the region occupies a large part of the surface of the epitaxial layer. Furthermore, an uneven surface is caused in the epitaxial layer, so that disconnections in the aluminum-wired layer or the like formed thereon are frequently caused.